[sram] assertion for capability write tags being the same on both beats
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- Dominant language
- SystemVerilog
- Stars
- 38
- Forks
- 21
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 14
Description
A capability write consists of 2 beats where each beat contains data and a tag bit. The capability only has 1 tag bit associated with it. The current behavior is that for a 2 beat capability write, the tag of only the last beat is considered (the second beat overwrites the first). This was brought up as a potential issue. Although the CVA6 always drives the tag on both bits the same, an the debug module doesnt drive the tag at all, it would still be good to eventually add an assertion that checks that both of the tags are the same on both beats.
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Research direction
The issue does not name a file or test; start by locating the capability write handling and existing assertions in the SystemVerilog sources. Add an assertion that the tag bits on both beats of a two-beat capability write match, and verify it covers the CVA6 and debug-module write paths described.
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Assessment
- Domain
- security
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Active
- Clarity
- Mostly clear
- Newbie friendliness
- 55/100