`prim_ram_1p.sv` can behave inconsistently for synthesis/simulation

prim_ram_1p.sv describes one-port RAM primitive.

The generic implementation (prim_generic/rtl/prim_ram_1p.sv) supports write masks of arbitrary granularity

The Xilinx implementation has a generate if/else constructs that switches between two possible implementation
The current configuration uses the same implementation as the generic which is fine
If the configuration is changed it switches to an implementation that does not support write masks

This strikes me as a major verification hazard - a primitive should never have different behaviour in simulation vs. synthesis.

This has already been fixed upstream in OpenTitan and the fix should be vendored in

Compare the Xilinx prim_ram_1p.sv implementation with prim_generic/rtl/prim_ram_1p.sv, focusing on the generate branches and write-mask behavior. Check the corresponding upstream OpenTitan fix, then verify that the vendored implementation behaves consistently for synthesis and simulation under the available configurations.