lowRISC / lowRISC/mocha

Debug module DV - Chip-level integration tests + JTAG DMI agent

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Dominant language
SystemVerilog
Stars
38
Forks
21
Avg merge
2d 23h
Merged PRs (30d)
14

Description

Chip-level debug testpoints beyond the smoke (the smoke is tracked in #141). The debug module is the raw PULP `dm_top` + `dmi_jtag`, not the OpenTitan `rv_dm` wrapper.

Prerequisite: connect a JTAG DMI agent (the vendored `hw/vendor/lowrisc_ip/dv/sv/jtag_agent` + `jtag_dmi_agent`) to the chip JTAG pins, which are currently tied off in `hw/top_chip/dv/tb/tb.sv`.

Testpoints (all V2, placeholders registered):
- `chip_rv_dm_ndm_reset` (`rv_dm_ndm_reset_req`, `rv_dm_ndm_reset_req_when_cpu_halted`)
- `chip_rv_dm_sba` (`rv_dm_sba_access` / `rv_dm_sba_access_cheri`)
- `chip_rv_dm_access_after_wakeup` (`rv_dm_access_after_wakeup`)
- `chip_rv_dm_access_after_escalation_reset` (`rv_dm_access_after_escalation_reset`)

Open questions for the debug/reset specialist that gate the pass/fail wording: (a) does the debug module survive its own NDM reset, given `rst_debug_n` is parented on `rst_sys_src_n` (the system-reset tree the NDM reset drives); (b) is debug meant to be available during low power, given the DM is clocked by `clk_main_infra` which gates in sleep; (c) is unconditional JTAG debug intended, or should it be gated by lifecycle state / authentication; (d) debug-mode CHERI behaviour (PCC for debug-ROM fetch, and capability-register tag access via abstract commands); (e) confirm the SBA-to-memory tag behaviour (the DM master drives AXI user=0, so SBA writes clear capability tags and reads cannot observe tag validity).

`chip_rv_dm_access_after_escalation_reset` is additionally blocked on alert_handler integration (#270).

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First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start with hw/top_chip/dv/tb/tb.sv and the vendored hw/vendor/lowrisc_ip/dv/sv/jtag_agent and jtag_dmi_agent, then review the four registered V2 testpoints. Resolve the listed reset, low-power, authentication, CHERI, and SBA tag-behavior questions with the debug/reset specialist; escalation-reset coverage also depends on #270. Done means chip-level JTAG DMI integration and defined pass/fail tests for the testpoints.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, security, testing
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Quiet
Clarity
Needs clarification
Newbie friendliness
25/100

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