Top level DV - Clock-gating and power-management tests

Chip-level tests for the clock and power managers, backed by bound clock-activity assertions (relates to #152). All V2, placeholders registered in hw/top_chip/dv/top_chip_sim_cfg.hjson.

Testpoints:

• chip_clkmgr_clock_gating: SW gates the gateable peripheral clock and hints the hintable main clock; a bound assertion sampled on an always-on reference clock confirms each clock output goes flat while gated and toggles again once re-enabled.
• chip_pwrmgr_wakeup: SW enters low power, the sequence injects a wakeup, and the test confirms the chip exits low power, the wakeup interrupt is delivered via the PLIC, and PWRMGR_WAKE_INFO identifies the source.
• chip_pwrmgr_lowpower_quiescent: during low power, bound assertions confirm clk_main_infra and clk_io_infra show no edges while clk_io_powerup keeps toggling, then all resume after wakeup.

Note: RTL functional simulation cannot measure power; the clock-flat check is the RTL-level proxy. True power-off (isolation, retention, leakage) is a power-aware gate-level signoff activity, out of scope here.

Start with the V2 placeholders in hw/top_chip/dv/top_chip_sim_cfg.hjson and review related issue #152. Implement the three named top-level testpoints for clock gating, wakeup delivery and low-power quiescence, using bound clock-activity assertions. Done means the tests cover the listed behaviors and resume conditions without claiming true power-off signoff.