Tag Controller - Block-level DV for V1
Open
@martin-velay is already working on this.
Since Jul 17, 2026.
- Dominant language
- SystemVerilog
- Stars
- 38
- Forks
- 21
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 14
Description
Build a simple test harness to verify that data written to DRAM with or without a tag is correctly read with its corresponding tag (sanity check only).
Look at whether this is reusable: https://github.com/openhwgroup/cv-hpdcache-verif
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- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
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