SPI clock pin missing timing constraints
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@raylau1 is already working on this.
Since Jul 9, 2026.
- Dominant language
- SystemVerilog
- Stars
- 38
- Forks
- 21
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 14
Description
No clock constraint has been added to the SPI sck pin. This means that all paths between the SPI clock and Mocha clock are not timed.
The csb pin is also treated as a clock and should have a clock constraint.
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