Warn if Verilator GPIO DPI model output[31] is toggled
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- Dominant language
- SystemVerilog
- Stars
- 38
- Forks
- 21
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 14
Description
The system GPIO input[31] line is connected to the microSD card detect feature of the Genesys 2 (FPGA) and SD card DPI model (Verilator), which means that in the Verilator testbench the GPIO DPI model output[31] line does not drive anything. Perhaps we want to add some logic to detect if someone attempts to toggle that line, and warn them that it will not do anything.
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Research direction
Start in the Verilator testbench's GPIO DPI model and trace handling of output[31] alongside the SD card DPI model. Add a warning when that line is toggled, and verify the testbench reports it without changing other GPIO behavior.
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Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 55/100