lowRISC / lowRISC/mocha

I2C DV -- Device TX-RX test

Open
#509 4 comments 0 reactions 1 assignee View on GitHub

@KinzaQamar is already working on this.

Since May 7, 2026.

  • #633 by @KinzaQamar — open
Dominant language
SystemVerilog
Stars
38
Forks
21
Avg merge
2d 23h
Merged PRs (30d)
14

Description

Write a vseq that will act as a host to send write and read transfer. At the end, contains some self checking mechanism to compare the data written is equal to data received

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