D1 sign-off: Debug module
Open
Nobody has claimed this yet.
- Dominant language
- SystemVerilog
- Stars
- 38
- Forks
- 21
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 14
Description
Do sign-off based on the D1 checklist.
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the linked D1 design sign-off checklist in doc/proj/stages.md and review its requirements for the Debug module. Inspect the module against each checklist item and complete the sign-off when all criteria are addressed.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, security
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100