Verilator memory sizes defined by RDL
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enhancement
- Dominant language
- SystemVerilog
- Stars
- 38
- Forks
- 21
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 14
Description
We should use the memory sizes defined by RDL instead of manually providing them to Verilator.
This issue was inspired by: https://github.com/lowRISC/mocha/pull/454#discussion_r3123269442
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating where memory sizes are manually provided to Verilator and where the RDL definitions are available. Trace how those values reach the simulation setup, then verify that the generated or configured sizes come from RDL without breaking the existing Verilator flow.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Refactor
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 52/100