Capability reset strategy
Open
Nobody has claimed this yet.
- Dominant language
- SystemVerilog
- Stars
- 38
- Forks
- 21
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 14
Description
Across both SRAM and DRAM.
When there is a software or external reset the tags in the SRAM and DRAM should be cleared.
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
No files, tests, or entry points are named in the issue, so first locate the SRAM and DRAM tag logic and the software and external reset paths. Trace how each reset reaches both memories. Done means tags in both SRAM and DRAM are cleared after either reset, with verification covering both reset sources.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, security
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Needs clarification
- Newbie friendliness
- 45/100