[fpga] Genesys2 top-level port names don't match schematic names
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- Dominant language
- SystemVerilog
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- 38
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- 21
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Description
Before we go too much further, I think it is worth considering whether we should switch to naming the ports in chip_mocha_genesys2.sv and pins_genesys2.xdc after the corresponding net name on the Genesys2 schematic rather than the current mixed approach (for which I'm partly to blame).
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Research direction
Compare the port names in chip_mocha_genesys2.sv and pins_genesys2.xdc with the corresponding net names on the Genesys2 schematic. Determine the complete naming convention and update both files so each port and pin uses its matching schematic net name; done means the mappings are consistent.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Refactor
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Quiet
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100