[Test] Uart interrupt
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@ziuziakowska is already working on this.
Since Dec 23, 2025.
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- SystemVerilog
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Description
Use test register [INTR_TEST](https://opentitan.org/book/hw/ip/uart/doc/registers.html#intr_test) to trigger the interrupt and check using [INTR_STATE](https://opentitan.org/book/hw/ip/uart/doc/registers.html#intr_state)
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