PLIC DV - V1 signoff
Open
- Dominant language
- SystemVerilog
- Stars
- 38
- Forks
- 21
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 14
Description
This issue has no description.
Contributor guide
No contributing guide indexed for this repository
Research direction
The issue has no body, files, tests, or entry point. Start by locating the PLIC design-verification work and the V1 signoff criteria; what counts as done is unclear until those criteria and required checks are identified.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 10/100