Top level DV - Assertions
Open
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- Dominant language
- SystemVerilog
- Stars
- 38
- Forks
- 21
- Avg merge
- 2d 23h
- Merged PRs (30d)
- 14
Description
Create or import (with binds) some assertions to check some basic behaviours like around the AXI Xbar for example or others coming from OT blocks if exist
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue does not name any files, tests, or verification entry points. Start by locating the top-level design-verification setup and the AXI Xbar or OT blocks, then determine which existing assertion patterns and bind mechanisms apply; done means basic behavioral assertions are created or imported and run in verification.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing-qa
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100