NastiIO bus width

For this version, would it be possible to change the bus width size of mem_nasti interface with the memory controller from 64 to 128 bits?

For instance, changing 64 to 128 below:

```

RD_PRI_REG
30
64
4
0

```

Start by locating the mem_nasti interface, memory controller, and the AXIParameters block shown in the issue. Trace where the 64-bit data width is defined and verify all connected interfaces and generated outputs remain compatible after changing it to 128 bits.

Written by the indexing model from the issue text.