Change in bus width for NastiIO

Would it be possible to change the bus width size of NastiIO fron 64 bits to 128bits? That would apply to nasti.r.bits.data and nasti.w.bits.data specifically. The purpose is being to perform read and write to DDR in 128bits instead of 64.
Any advice?

Start by locating the NastiIO definition and tracing nasti.r.bits.data and nasti.w.bits.data through the DDR path. Check how the existing 64-bit width is specified and propagated; done means reads and writes use 128-bit data consistently without breaking connected interfaces. No file or test is named in the issue.

Written by the indexing model from the issue text.