how to add new instruction

I try to add a new instruction and run the simulation using spikes.

I did the following process.

1. make .h file

at  $TOP/riscv-tools/riscv-isa-sim/riscv/insns /

: cp divw.h newinst.h
: gedit newinst.h

require_extension ('M');
require_rv64;
sReg_t lhs = sext32 (RS1);
sReg_t rhs = sext32 (RS2);
if (rhs == 0)
  WRITE_RD (UINT64_MAX);
else
  WRITE_RD (sext32 (lhs + rhs + 100));

And then saved it.

2. Adding opcdoe

at $TOP/riscv-tools/riscv-isa-sim/riscv-tools/riscv-opcodes

: gedit opcodes

newinst rd rs1 rs2 31..25 ​​= 1 14..12 = 1 6..2 = 0x0E 1..0 = 3

I added this phrase.

I did a [make install] and I checked that the instruciton do not overlap.

3. spike rebuild

: cd $ TOP / riscv-tools
: ./build.sh

I'm trying to rebuild a command by executing an error

Then the following error occurred.

In file included from ../riscv/mmu.h:7:0:0,
                 from ../riscv/insn_template.h:3:
../riscv/trap.h: In constructor 'trap_instruction_address_misaligned :: trap_instruction_address_misaligned (reg_t)':
../riscv/trap.h:45:18: error: 'CAUSE_MISALIGNED_FETCH' was not declared in this scope
 DECLARE_MEM_TRAP (CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
                  ^
../riscv/trap.h:41:41: note: in definition of macro 'DECLARE_MEM_TRAP'
   trap _ ## x (reg_t badvaddr): mem_trap_t (n, badvaddr) {}
                                         ^
../riscv/trap.h: In constructor 'trap_instruction_access_fault :: trap_instruction_access_fault (reg_t)':
../riscv/trap.h:46:18: error: 'CAUSE_FAULT_FETCH' was not declared in this scope
 DECLARE_MEM_TRAP (CAUSE_FAULT_FETCH, instruction_access_fault)
                  ^
../riscv/trap.h:41:41: note: in definition of macro 'DECLARE_MEM_TRAP'
   trap _ ## x (reg_t badvaddr): mem_trap_t (n, badvaddr) {}
                                         ^
../riscv/trap.h: In constructor 'trap_illegal_instruction :: trap_illegal_instruction ()':
../riscv/trap.h:47:14: error: 'CAUSE_ILLEGAL_INSTRUCTION' was not declared in this scope
 DECLARE_TRAP (CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)

Q : Is there something wrong with the process?
or how can I fix the error and run a new instruction with spike?

Start by reviewing riscv/insns/newinst.h, the added entry in riscv-opcodes/opcodes, and the build.sh rebuild path. Inspect riscv/trap.h and the reported missing cause constants, then rerun the build and confirm that the new instruction can be simulated with Spike.