lowRISC / lowRISC/lowrisc-chip
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- Dominant language
- SystemVerilog
- Stars
- 601
- Forks
- 147
- PR merge metrics
- No merged PRs in 30d
Description
Hi I am evaluating various RISCV Cores. I am getting the following results for Lowrisc V.4.0.
Core | ISA | Bit | Pipeline | LUTs | LUT RAMs | LUT FFs | BRAM | Power µW/MHz | Dhrystone DMIPS/ MHz | Coremark /MHz | Target FPGA
-- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | --
Lowrisc_64 | RV64IMAFD | 64 | 6 | 49904 | 1943 | 26788 | 71 | 0.063 | 1.72 | 3.06 | Nexys-4 DDR
Is these results are correct or not? Can you share these information to me.
Can you update Dhrystone performance for Rocket Core?
I want to change the cache memory size for LowRISC. So can you share how to change the cache memory for LowRISC?
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First steps
- Read the whole issue, then the project's contributing guide.
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Research direction
The issue contains a LowrISC benchmark table and asks for validation, Rocket Core Dhrystone data, and instructions for changing LowRISC cache size, but names no files, tests, or entry points. Start by locating the relevant benchmark and cache-configuration documentation; done means the comparison is validated or corrected and the requested cache guidance is documented.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, performance
- Issue type
- Documentation
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100