lowRISC / lowRISC/lowrisc-chip
+waitdebug problem
@wallento is already working on this.
Since Aug 24, 2017.
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- SystemVerilog
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Description
I have managed to build the simulation via:
`make CONFIG=DebugConfig` in `vsim `directory
next I would like launch the RTL simulation and but the debug tool couldnt connect correctly when I run:
`./DebugConfig-sim +waitdebug`
of which I didnt manage to see the output on the terminal. Basically there is nothing printed at all.
`Glip TCP DPI listening on port 23000 and 23001`
I have successfully build both **Glip Software** and **Open SoC Debug software**
and also I tried to connect the daemon on the second terminal
`opensocdebugd tcp`
I observed the following outcome:
```
Open SoC Debug Daemon
Backend: tcp
glip: glip_open: Cannot open backend
glip: glip_write_b: No connection; you need to call glip_open() first!
glip: glip_read_b: No connection; you need to call glip_open() first!
opensocdebugd: ../../src/connection-standalone.c:67: receiver_thread_function: Assertion `rv == 0' failed.
Aborted (core dumped)
```
any advice what could have possibly gone wrong?
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