lowRISC / lowRISC/lowrisc-chip
ERROR: [Board 49-71] The board_part definition was not found for digilentinc.com:nexys4_ddr:part0:1.1.
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- SystemVerilog
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Description
After modifying the Makefile PATH for vivado, it works for the previous issue but soon have another.
Please help for any hint.
vivado -mode batch -source tcl/run.tcl
****** Vivado v2018.3 (64-bit)
**** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018
**** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
CRITICAL WARNING: [Common 17-741] No write access right to the local Tcl store at '/home/nicolast0604/.Xilinx/Vivado/2018.3/XilinxTclStore'. XilinxTclStore is reverted to the installation area. If you want to use local Tcl Store, please change the access right and relaunch Vivado.
source tcl/run.tcl
# set partNumber $::env(XILINX_PART)
# set boardName $::env(XILINX_BOARD)
# set ipName xlnx_axi_clock_converter
# create_project $ipName $::env(BOARD) -force -part $partNumber
# set_property board_part $boardName [current_project]
ERROR: [Board 49-71] The board_part definition was not found for digilentinc.com:nexys4_ddr:part0:1.1. The project's board_part property was not set, but the project's part property was set to xc7a100tcsg324-1. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.
INFO: [Common 17-206] Exiting Vivado at Sun Jun 6 21:04:43 2021...
../common.mk:2: recipe for target 'all' failed
make[3]: *** [all] Error 1
make[3]: Leaving directory '/home/nicolast0604/lowrisc-chip-ariane-v0.7/fpga/xilinx/xlnx_axi_clock_converter'
Makefile:45: recipe for target 'work-fpga/nexys4_ddr_ariane/xlnx_axi_clock_converter.xci' failed
make[2]: *** [work-fpga/nexys4_ddr_ariane/xlnx_axi_clock_converter.xci] Error 2
make[2]: Leaving directory '/home/nicolast0604/lowrisc-chip-ariane-v0.7/fpga'
Makefile:44: recipe for target 'fpga/work-fpga/nexys4_ddr_ariane/ariane_xilinx.mcs' failed
make[1]: *** [fpga/work-fpga/nexys4_ddr_ariane/ariane_xilinx.mcs] Error 2
make[1]: Leaving directory '/home/nicolast0604/lowrisc-chip-ariane-v0.7'
Contributor guide
No contributing guide indexed for this repository
Research direction
Start with tcl/run.tcl and the Makefile environment variables that set XILINX_PART and XILINX_BOARD. Run Vivado's get_board_parts command and inspect the board.repoPaths setting and installed board definitions. Done means the xlnx_axi_clock_converter target completes without the board_part error.
Written by the indexing model from the issue text.
Assessment
- Domain
- build-system, embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100