loading bitstream file into FPGA but no reaction happened on Tera Term

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Hi, I am working on the hello world test of "lowrisc-chip". The branch that I am working on is kc705_update. The problem is that I can generate the bitstream file and combine it with the "hello world" test hex file, but when I load it into my FPGA, there is no reaction on the terminal.

The board that I am using is Xilinx Atrix-7 AC701 board. I made a lot of modifications based on the "kc705_update" branch including pin mapping, MIG, BRAM controller, etc. The whole synthesis and implementation look normal. Since I don't have Xilinx Kintex KC705 board, I am not sure whether this "kc705_update" is correct or not. My final target is to build a RISC-V CPU on Xilinx AC701 board and port Linux on it, so I choose KC705 board project as a base.

For now, after checking Xilinx official BIST (Build In Self Test), I guess the problem is the test .c file is wrong. But I am not sure. Thanks for your help.

Start with the kc705_update board project and the bitstream plus hello world hex loading workflow, comparing the AC701 setup with the KC705 assumptions. Inspect the pin mapping, MIG, BRAM controller, and hello world test .c file, then check the Tera Term output. Done means identifying whether the missing response comes from the board configuration or the test software.

Written by the indexing model from the issue text.