How to add new peripheral to Refresh 0.6 SoC

I am trying to add new peripheral to SoC on Refresh 0.6, I created a vivado project and examined codes. I think right place to add a peripheral is perip_soc.sv file. But i cannot see axi interface signals or addresses for peripherals. Is there something i am missing?

The issue points to perip_soc.sv and a Vivado project; begin by tracing how AXI interfaces and peripheral addresses are defined around that entry point. No peripheral specification or test target is provided, so confirm the integration path and expected address map with maintainers before implementing. Done means the new peripheral is integrated with a defined address and verified in the project.

Written by the indexing model from the issue text.