lowRISC / lowRISC/lowrisc-chip
Tilelink to Wishbone bridge
Open
- Dominant language
- SystemVerilog
- Stars
- 601
- Forks
- 147
- PR merge metrics
- No merged PRs in 30d
Description
Hello,
I saw there is a project for Tilelink to Wishbone bridge in lowRISC project. Is it open source? How can I access them if it is open source?
Thank you in advance,
Contributor guide
No contributing guide indexed for this repository
Research direction
The issue names no source file, test, or entry point; begin by checking the repository and lowRISC project documentation for the referenced TileLink-to-Wishbone bridge. Done would mean documenting whether the project is open source and where it can be accessed, but the issue provides no implementation scope.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation
- Issue type
- Documentation
- Difficulty
- 1/5
- Estimated time
- Under an hour
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 1/100