lowRISC / lowRISC/lowrisc-chip
L1 Cache replacement policy
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- Dominant language
- SystemVerilog
- Stars
- 601
- Forks
- 147
- PR merge metrics
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Description
Hi all,
As far as I can see from the Chisel files the L1 D cache replacement policy is defined to be Random replacement. The Pseudo LRU policies are defined just for higher level caches and my attempt to port them to L1 was not fruitfull.
I wanted to ask if there is any quick way implementing another policy than the random replacement for the L1 and why has only this policy been implemented? Is there a specific reason (performance-wise e.tc.) ?
Thanks in advance!
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the Chisel files that define the L1 D-cache replacement policy and compare them with the higher-level Pseudo-LRU implementation. Clarify which alternate policy is desired, why Random replacement was chosen for L1, and what implementation and validation would count as complete.
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Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100