lowRISC / lowRISC/ibex

Investigate special case direct forwarding from loads

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#976 1 comment 0 reactions 0 assignees View on GitHub

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Component:RTL Type:Enhancement
Dominant language
SystemVerilog
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Merged PRs (30d)
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Description

When using the writeback stage any instruction directly following a load that uses the results of that load must stall at least one cycle (or more if the load takes more than one cycle to get its data) so the required data can be written to the register file. We do not directly forward the load data into the dependent instruction for timing reasons (read data coming in would have to be fed directly to the ALU).

There are particular cases of direct forwarding of load data into dependent instructions that may be possible, where the instruction is doing something simple with the data.

A specific example would be branches using an equal/not-equal to zero condition or potentially the more general equal/not-equal to a register condition. Implementing this would require an extra comparator tied directly to the incoming memory data.

This can be useful in tight pointer chasing loops e.g:

while(list_node && (list_node->n != search_val))
  list_node = list_node->next;

One of the things coremark does is such a pointer chasing loop.

We should investigate how practical this is and what other simple forward cases may exist.

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First steps

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Research direction

Review the writeback stage and the load-dependent instruction path described in the issue; no file or test names are provided, so locate those entry points first. Use the CoreMark pointer-chasing loop as the workload, with done defined as a conclusion about practicality and other simple forwarding cases.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, performance
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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