Testing for RISC-V trace interface
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- SystemVerilog
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Description
#899 is tracking progress towards adding a RISC-V Trace Specification-compliant interface to Ibex. It would be good to have some kind of test for this feature as well to check that the signals match what we expect to trace.
Probably end-to-end tests against a golden model are sufficient for a start, i.e. feeding a program binary, running it, and comparing the traced data against a golden reference.
I asked at riscv/riscv-trace-spec#41 if something like that already exists, otherwise we'll need to invent something ourselves.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reviewing #899 and the RISC-V Trace Specification discussion at riscv/riscv-trace-spec#41 to determine whether an existing test approach is available. Define an end-to-end test that feeds a program binary to Ibex and compares its traced data and signals with a golden reference.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100