Add RISC-V Trace Specification-compliant interface

Nobody has claimed this yet.

The [RISC-V Trace Specification](https://github.com/riscv/riscv-trace-spec/blob/master/riscv-trace-spec.pdf) provides a standardized way to extend a RISC-V CPU Core with runtime instruction tracing functionality, as provided by ARM CoreSight or Nexus 5001.

The specification also includes a standardized interface between the core and the rest of the tracing infrastructure. This interface is intended to be used by all compliant tracing systems.

The goal of this issue is to add this interface to Ibex.

Related Work:
- The RVFI interface in Ibex carries similar data, but is intended for simulation use, while the RV Trace Interface is meant for synthesis.
- The newer SweRV cores also support this interface, see https://github.com/chipsalliance/Cores-SweRV-EL2/blob/master/design/el2_swerv.sv#L37 and https://github.com/chipsalliance/Cores-SweRV-EL2/blob/e1301d4d47bc6bde5f9f0c0443e2ee091fbcd3aa/design/dec/el2_dec.sv#L422.

I couldn't find any tests with the expected trace signal output. I asked at https://github.com/riscv/riscv-trace-spec/issues/41, let's see if there's something that already exists, of if we need to create such tests ourselves.

@timeprints will work on the implementation of this during her GSoC.

Start with the RISC-V Trace Specification and Ibex's RVFI interface, then compare the referenced SweRV files, especially design/el2_swerv.sv and design/dec/el2_dec.sv. Determine how the trace interface maps to Ibex's core signals and whether expected trace-output tests exist. Done means Ibex exposes a specification-compliant synthesizable interface with suitable tests.

Written by the indexing model from the issue text.