[rtl] Dummy instruction enhancements
Open
@tomeroberts is already working on this.
Since May 21, 2020.
Type:Enhancement
- Dominant language
- SystemVerilog
- Stars
- 2.1k
- Forks
- 810
- Avg merge
- 5d 23h
- Merged PRs (30d)
- 9
Description
- Wider control of insertion frequency, all the way down every other instruction
- Add dummy instructions when IF stage stalls to hide I$ timing side-channel
- Add some scrambling to LFSR output
- Replace NOPs with dummy instructions (idea from CG since algorithm writers sometimes add NOPs for obfuscation, but their power signature can be a bit obvious)
- More software control over the types of instructions inserted and their weighting and/or
- Bias instruction type towards recently executed actual instructions
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Assessment
This issue has not been assessed yet.