Test trap precision
Open
Nobody has claimed this yet.
Component:DV
Type:Enhancement
- Dominant language
- SystemVerilog
- Stars
- 2.1k
- Forks
- 810
- Avg merge
- 5d 23h
- Merged PRs (30d)
- 9
Description
Add DV to ensure that traps are as precise as we expect them to be. This requires the expectations to be documented first in #86.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Read issue #86 first, since this issue depends on its documented expectations. Then locate the project's design-verification entry point for trap behavior; done means verification demonstrates that traps meet those expectations with precise outcomes.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, testing
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100