Document trap precision
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Component:Doc
Component:RTL
Type:Task
- Dominant language
- SystemVerilog
- Stars
- 2.1k
- Forks
- 810
- Avg merge
- 5d 23h
- Merged PRs (30d)
- 9
Description
The RISC-V spec gives us some flexibility how precise traps should be. We need to document our current behavior.
I'd expect all traps to be precise, but we should double-check with the code.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reading the trap-handling code and the relevant RISC-V specification sections. Verify whether the implementation makes all traps precise, then document the observed behavior and any distinctions or exceptions in the appropriate project documentation.
Written by the indexing model from the issue text.
Assessment
- Domain
- documentation
- Issue type
- Documentation
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100