lowRISC / lowRISC/ibex

Long path through multdiv into IF stage

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Component:RTL Type:Enhancement
Dominant language
SystemVerilog
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Description

During his Zbt work #746 @ganoam noted that there is a long path from the register_file -> *multdiv* -> alu -> ex_block/branch_decision_o -> controller -> IF stage.

The strange thing is that while the path through multdiv and alu is expected (we use the adder for divisions), the combined path should never end up in the controller, branch decision, IF (these ops only depends on the alu). So my suggestion was to qualify the branch decision in the controller with an early signal (the branch decision should never matter if we are doing a multdiv). But this did not really help.

Maybe @tomroberts-lowrisc or @GregAC have some ideas?

The timing report can be found [here](https://github.com/ganoam/ibex/blob/bitmanip-devel-zbt/reports/bitmanip-zbt-pr/33bitshifter_adderbinmux_optimized/RV32B0_3stage_btalu_2_ns/post_synth_timing.rpt).

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First steps

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  3. Fork the repository and make your change on a branch.
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Research direction

Start with the linked post-synthesis timing report and trace the register_file → multdiv → alu → ex_block/branch_decision_o → controller → IF path. Read the relevant pipeline and branch-decision logic to determine why multdiv operations still reach the controller and IF stage. Done means the multdiv timing path no longer includes that unnecessary combined path, with the result confirmed in a timing report.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot
Issue type
Bug
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

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