[tracking] Synthesize Ibex with Yosys

Nobody has claimed this yet.

*This is a tracking bug. This description will be updated to reflect the current state of affairs. Comment if you have suggestions or updates.*

[Yosys](http://www.clifford.at/yosys/) currently supports only a limited subset of SystemVerilog, which isn't sufficient to parse Ibex. This issue tracks the outstanding issues. We are generally open to find a common ground between tools, but only as long as it doesn't affect code quality and correctness. This means some issues will be resolved upstream in Yosys, while others might be worked around in Ibex.

Updated 2020-08-20. We're almost there, thanks to the work of @kgugala and others at Antmicro, and of course the Yosys reviewers!

We currently know of these issues which are still blocking us from synthesizing Ibex with Yosys:

- [ ] https://github.com/YosysHQ/yosys/pull/2331
- [x] https://github.com/YosysHQ/yosys/pull/2330
- [x] https://github.com/YosysHQ/yosys/pull/2329
- [x] https://github.com/YosysHQ/yosys/pull/2312
- [ ] https://github.com/YosysHQ/yosys/pull/2248

This is a tracking bug for synthesizing Ibex with Yosys; start by reviewing the unchecked Yosys pull requests linked in the description. Done means the remaining blockers are resolved or explicitly assigned to an upstream Yosys change or an Ibex workaround, and the checklist is updated.

Written by the indexing model from the issue text.