syn: Remove copy of prim_clock_gating.v and use shared version instead
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Component:RTL
Type:Task
- Dominant language
- SystemVerilog
- Stars
- 2.1k
- Forks
- 810
- Avg merge
- 5d 23h
- Merged PRs (30d)
- 9
Description
Having multiple versions of that file in the tree confuses users to pick the wrong one, so the one in `syn` should go.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start in the `syn` tree and locate its copy of `prim_clock_gating.v`, then identify the shared version it should use. Done means the duplicate is removed and the synthesis flow still references the shared file without selecting the wrong copy.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Refactor
- Difficulty
- 2/5
- Estimated time
- 1-3 hours
- Activity status
- Stale
- Clarity
- Clearly specified
- Newbie friendliness
- 45/100