Consider clear-dominant fetch FIFO payload updates
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- Dominant language
- SystemVerilog
- Stars
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Description
Local synthesis identifies fetch FIFO payload/error updates on the
taken-branch redirect path. Qualifying their enables with `!clear_i`
improves arrival time from 2.89 ns to 2.77 ns at a measured 0.44% area
cost.
The change has passed directed clear/push/pop testing, Ibex hello_test,
and a standalone SymbiYosys/Z3 proof.
Would this timing/area tradeoff and implementation-level payload
stability behavior be considered appropriate for an upstream RTL change?
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
No RTL file is named. Start by locating the fetch FIFO payload and error updates on the taken-branch redirect path, then review the directed clear/push/pop tests, Ibex hello_test, and the standalone SymbiYosys/Z3 proof. Done means the proposed enable qualification is evaluated for timing, area, payload stability, and upstream suitability.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, performance
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Active
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100