lowRISC / lowRISC/ibex

How to read RTL files in order properly with yosys + slang plugin Ibex. (not expert, just new here)

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Type:Question
Dominant language
SystemVerilog
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Description

**when i try to read all rtl files from ibex/rtl/*.sv , it shows errors like this:**

```
../ibex/rtl/ibex_csr.sv:9:10: error: 'prim_assert.sv': No such file or directory
`include "prim_assert.sv"
^~~~~~~~~~~~~~~~
../ibex/rtl/ibex_csr.sv:55:3: error: unknown macro or compiler directive '`ASSERT_KNOWN'
`ASSERT_KNOWN(IbexCSREnValid, wr_en_i)
^~~~~~~~~~~~~
../ibex/rtl/ibex_pmp.sv:5:10: error: 'dv_fcov_macros.svh': No such file or directory
`include "dv_fcov_macros.svh"
^~~~~~~~~~~~~~~~~~~~
../ibex/rtl/ibex_pmp.sv:255:5: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
`DV_FCOV_SIGNAL(logic, pmp_region_override,
^~~~~~~~~~~~~~~
../ibex/rtl/ibex_cs_registers.sv:10:10: error: 'prim_assert.sv': No such file or directory
`include "prim_assert.sv"
^~~~~~~~~~~~~~~~
../ibex/rtl/ibex_cs_registers.sv:1214:7: error: unknown macro or compiler directive '`ASSERT_INIT'
`ASSERT_INIT(PMPAddrRstLowBitsZero_A, PMPRstAddr[i][PMP_ADDR_MSB-PMPAddrWidth:0] == '0)
^~~~~~~~~~~~
../ibex/rtl/ibex_cs_registers.sv:1680:3: error: unknown macro or compiler directive '`ASSERT'
`ASSERT(IbexCsrOpEnRequiresAccess, csr_op_en_i |-> csr_access_i)
^~~~~~~
../ibex/rtl/ibex_multdiv_slow.sv:12:10: error: 'prim_assert.sv': No such file or directory
`include "prim_assert.sv"
^~~~~~~~~~~~~~~~
../ibex/rtl/ibex_multdiv_slow.sv:369:3: error: unknown macro or compiler directive '`ASSERT'
`ASSERT(IbexMultDivStateValid, md_state_q inside {
^~~~~~~
../ibex/rtl/ibex_controller.sv:10:10: error: 'prim_assert.sv': No such file or directory
`include "prim_assert.sv"
^~~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:11:10: error: 'dv_fcov_macros.svh': No such file or directory
`include "dv_fcov_macros.svh"
^~~~~~~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:207:3: error: unknown macro or compiler directive '`ASSERT'
`ASSERT(IllegalInsnOnlyIfInsnValid, illegal_insn_i |-> instr_valid_i)
^~~~~~~
../ibex/rtl/ibex_controller.sv:295:3: error: unknown macro or compiler directive '`ASSERT_IF'
`ASSERT_IF(IbexExceptionPrioOnehot,
^~~~~~~~~~
../ibex/rtl/ibex_controller.sv:898:3: error: unknown macro or compiler directive '`ASSERT'
`ASSERT(PipeEmptyOnIrq, ctrl_fsm_cs != IRQ_TAKEN & ctrl_fsm_ns == IRQ_TAKEN |->
^~~~~~~
../ibex/rtl/ibex_controller.sv:905:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
`DV_FCOV_SIGNAL(logic, all_debug_req, debug_req_i || debug_mode_q || debug_single_step_i)
^~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:906:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
`DV_FCOV_SIGNAL(logic, debug_wakeup, (ctrl_fsm_cs == SLEEP) & (ctrl_fsm_ns == FIRST_FETCH) &
^~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:908:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
`DV_FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN))
^~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:909:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
`DV_FCOV_SIGNAL(logic, debug_entry_if,
^~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:911:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
`DV_FCOV_SIGNAL(logic, debug_entry_id,
^~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:913:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
`DV_FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH))
```

**in ibex/rtl there are many missing files and modules linked to the files available at Vendor/lowrisc_ip/ip/prim/rtl.**

**so how to read RTL files in proper manner for Ibex synthesis? there are also other RTL files inside Vendor/lowrisc_ip/ip/prim/rtl & prim_generic/rtl**

**which rtl files should read first?**

**using SLANG plugin to read systemverilog files, instead of converting SV2V.**
(don't judge my English please}
i'm using **read_slang**
i'm also unable to understand proper order in which rtl files are written.
## My Environment

**EDA tool and version:** **yosys + slang**

**Operating system:**

**Version of the Ibex source code:**

Contributor guide

Open the contributing guide

First steps

  1. Read the whole issue, then the project's contributing guide.
  2. Comment on the issue to say you are picking it up — it saves two people doing the same work.
  3. Fork the repository and make your change on a branch.
  4. Open a pull request that references the issue number.

Research direction

Start by reviewing the Ibex RTL under ibex/rtl and the referenced Vendor/lowrisc_ip/ip/prim/rtl and prim_generic/rtl directories, then inspect how read_slang is invoked with Yosys. Document the required source and include paths, any relevant RTL ordering, and a reproducible command that reads the design without the reported missing-file and macro errors.

Written by the indexing model from the issue text.

Assessment

Domain
embedded-iot, tooling
Issue type
Documentation
Difficulty
4/5
Estimated time
3-5 days
Activity status
Active
Clarity
Needs clarification
Newbie friendliness
38/100

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