Surelog syntax error when parsing ibex_core.f (Syntax error: no viable alternative at input 'ibex_top.',)

I am trying to parse the Ibex RTL using Surelog (Synlig). The first frontend execution completes with warnings only, but the second execution fails with a syntax error while parsing ibex_core.f

Below is the exact content of my filelist (ibex_core.f):
../rtl/ibex_top.sv
../rtl/ibex_pkg.sv
../rtl/ibex_alu.sv
../rtl/ibex_compressed_decoder.sv
../rtl/ibex_controller.sv
../rtl/ibex_counter.sv
../rtl/ibex_cs_registers.sv
../rtl/ibex_decoder.sv
../rtl/ibex_ex_block.sv
../rtl/ibex_id_stage.sv
../rtl/ibex_if_stage.sv
../rtl/ibex_load_store_unit.sv
../rtl/ibex_multdiv_slow.sv
../rtl/ibex_multdiv_fast.sv
../rtl/ibex_prefetch_buffer.sv
../rtl/ibex_fetch_fifo.sv
../rtl/ibex_register_file_ff.sv
../rtl/ibex_core.sv

To ensure there are no hidden characters, I ran:
cat -A /home/mysha/Project/design/Ibex_RISC-V_Core/rtl/ibex_core.f | head -n 10
Output:
../rtl/ibex_top.sv$
../rtl/ibex_pkg.sv$
../rtl/ibex_alu.sv$
../rtl/ibex_compressed_decoder.sv$
../rtl/ibex_controller.sv$
../rtl/ibex_counter.sv$
../rtl/ibex_cs_registers.sv$
../rtl/ibex_decoder.sv$
../rtl/ibex_ex_block.sv$
../rtl/ibex_id_stage.sv$

I added the following commands to my yosys_run_synth.tcl file:
yosys "plugin -i /home/mysha/synlig/build/release/systemverilog-plugin/systemverilog.so"
yosys "read_systemverilog -defer -f ../rtl/ibex_core.f -Ipath /home/mysha/Project/design/Ibex_RISC-V_Core/rtl/prim/prim_assert.sv"
yosys "read_systemverilog -link"

Problem 1: Frontend Execution (Warnings Only)
Include Path Warning:
[WRN:CM0005] Include path "/home/mysha/Project/design/Ibex_RISC-V_Core/syn/path" does not exist.

Macro Warnings:
[WRN:PP0113] /home/mysha/Project/design/Ibex_RISC-V_Core/rtl/prim/prim_assert_dummy_macros.svh:8:9: Unused macro argument "__name".
[WRN:PP0113] /home/mysha/Project/design/Ibex_RISC-V_Core/rtl/prim/prim_assert_dummy_macros.svh:8:9: Unused macro argument "__prop".

Frontend Summary:
[ FATAL] : 0
[ SYNTAX] : 0
[ ERROR] : 0
[WARNING] : 56
[ NOTE] : 0

Problem 2: Filelist parsing error
3. Executing SystemVerilog frontend.
[INF:CM0023] Creating log file "/home/mysha/Project/design/Ibex_RISC-V_Core/syn/slpp_all/surelog.log".
[SNT:PA0207] /home/mysha/Project/design/Ibex_RISC-V_Core/rtl/ibex_core.f:4:8: Syntax error: no viable alternative at input 'ibex_top.',
ibex_top.sv
^--.
[ FATAL] : 0
[ SYNTAX] : 1
[ ERROR] : 0
[WARNING] : 0
[ NOTE] : 0
ERROR: Error when parsing design. Aborting!
At this stage, I’m not certain what the next step should be. Any guidance would be greatly appreciated. Thank you.

Start with rtl/ibex_core.f, yosys_run_synth.tcl, and the Surelog log at syn/slpp_all/surelog.log. Reproduce both read_systemverilog invocations and compare the successful first frontend execution with the failing filelist parse; done means the supplied filelist is accepted without the reported syntax error.