PLIC claim process with Ibex

Nobody has claimed this yet.

In the RISC-V Platform-Level Interrupt Controller (PLIC) Specification, I read a paragraph in Chapter 8, Interrupt Claim Process:

“It is always legal for a hart to perform a claim even if the EIP is not set. In particular, a hart could set the threshold value to maximum to disable interrupt notifications and instead poll for active interrupts using periodic claim requests, though a simpler approach to implement polling would be to clear the external interrupt enable in the corresponding xie register for privilege mode x.”

My understanding is as follows:
This describes an optional interrupt-handling mechanism. When I set the threshold to the maximum value (thus disabling EIP notifications from the PLIC), the CPU can run a periodic loop to read the claim register. If the returned value is non-zero (i.e., the ID of the interrupt source with the highest priority), the CPU then handles the interrupt as usual.

I set up the PLIC as follows:

Set priorities for sources 0 to 6 to values 0 to 6, respectively

Enable all interrupt sources in the PLIC enable registers

Set the threshold to 7

Assert interrupt sources 0 to 6 (pending[0:6] = 1)

Use lw to read the claim/complete register

According to the specification, I expected the value loaded from the claim/complete register to be the ID of the highest-priority interrupt source (ID = 6). However, I only receive a value of zero. Is this legal behavior? Or am I misunderstanding the specification?

Start with Chapter 8 of the RISC-V PLIC Specification and compare its Interrupt Claim Process with the reported setup: priorities, enables, threshold 7, pending sources 0–6, and the claim/complete register read using lw. Determine whether a zero result is permitted and whether the report identifies an Ibex behavior requiring a code or documentation change.

Written by the indexing model from the issue text.