[SecureIbex] OpenOCD attach fails when SecureIbex=1 (works when SecureIbex=0)

Nobody has claimed this yet.

## My Environment

**EDA tool and version:**

Verilator 4.228 2022-10-01 rev v4.228
Open On-Chip Debugger 0.12.0

**Operating system:**

Ubuntu 24.04.3

**Version of the Ibex source code:**

8084e1bd054fd7c6b09bc51694b7b261d13286f2

**Integration**
Ibex core integrated with [pulp-platform/riscv-dbg](https://github.com/pulp-platform/riscv-dbg) environment.

## Problem Description
I am trying to connect Ibex to OpenOCD through the riscv-dbg infrastructure.
When the SecureIbex option is disabled (SecureIbex=0), OpenOCD can attach.
When the SecureIbex option is enabled (SecureIbex=1), OpenOCD fails to attach properly.

With SecureIbex=1:

OpenOCD reports errors such as:
`Error: unable to halt hart 0`
`Error: dmcontrol=0x80000001`
`Error: dmstatus =0x00000c82`
`Error: Fatal: Hart 0 failed to halt during examine()`

In waveforms, I can see debug_req_i asserted and the PC jumping to 0x1A110800 (DmHaltAddr).

With SecureIbex=0, instruction address sequence looks normal (0x1A11_0800 → 0x1A11_0804 → 0x1A11_0818 …).
With SecureIbex=1, instruction address sequence diverges (0x1A11_0800 → 0x1A11_0804 → 0x1A11_0808 → 0x1A11_0888 …).

Is there any known limitation or additional integration step required when using Ibex with riscv-dbg while SecureIbex is enabled?

With `SecureIbex=1`, `debug_req_i` is asserted and PC jumps to `0x1A110800`, but then the sequence diverges unexpectedly (`0x0800 → 0x0804 → 0x0808 → 0x0888 …`).
See attached waveform screenshot:

Start by reproducing the OpenOCD attach failure in the reported riscv-dbg integration with SecureIbex set to 1, then compare the debug_req_i and PC sequences against SecureIbex=0. Trace the divergent sequence around DmHaltAddr and determine whether a known limitation or additional integration step explains the failed hart halt.

Written by the indexing model from the issue text.