[dv/formal] Relax memory bounds for open source formal flow
Nobody has claimed this yet.
- Dominant language
- SystemVerilog
- Stars
- 2.1k
- Forks
- 810
- Avg merge
- 5d 23h
- Merged PRs (30d)
- 9
Description
Currently, in the OSS flow all memory operations are assumed to granted/responded to as soon as the protocol allows (immediately for `req_o/gnt_i` and after one cycle for `gnt_i/rvalid_i`).
For Jasper we allow anything between the minimum and a 10 cycle delay. Ideally we would do this for the OSS flow too.
In principle this should not be difficult, but it would be reasonable to expect a fairly significant slowdown on some properties, though hopefully not too many.
This _may_ be as simple as just running the flow with relaxed constraints and seeing what happens, or it may require SST work.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the OSS formal flow and its current memory-operation timing constraints, then compare them with the Jasper flow, which permits delays from the minimum through 10 cycles. Run the flow with relaxed constraints and check whether properties still complete and pass; investigate SST only if the constraint change is insufficient.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100