[rtl] Refactor register files to bring common logic together
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- SystemVerilog
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Description
We have 3 register file implementations, one flip-flop based, one latch based and one targetting FPGA implementation. They all duplicate various bits of security hardening logic. The register files should be refactored so the security hardening logic is in a common module as much as is possible and keeping the per-implementation logic to a minimum.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Locate the three register file implementations described in the issue and compare their duplicated security hardening logic. Refactor the shared logic into a common module while keeping implementation-specific logic minimal; done means the three implementations no longer duplicate the common hardening behavior.
Written by the indexing model from the issue text.
Assessment
- Domain
- security
- Issue type
- Refactor
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100