Ibex simple system cannot simulate with timing flag in Verilator

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## Observed Behavior

We synthesized the Ibex core using Yosys and when it is simulated with --timing flag in verilator (in .core file), then the simulation fails throwing an error "Active region did not converge". Can you please shed some light on this and advise me how to debug this issue?
## Expected Behavior

## Steps to reproduce the issue

* With the synthsized netlist, the Ibex simple system "Hello World" program is run with the -no-timing flag and it runs perfectly
* With the synthesized netlist, the same program with -timing flag throws error "Active region did not converge"
## My Environment

**EDA tool and version:**

Verilator version :- 5.018 and 5.026
**Operating system:**

Cent OS 7
**Version of the Ibex source code:**


Start by reproducing the Ibex simple system Hello World run with the synthesized netlist under Verilator 5.018 or 5.026, comparing the no-timing and timing-flag cases. The issue names no source files, tests, exact commands, or Ibex revision; done would require isolating the cause of the active-region convergence failure and documenting a reproducible result.

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