How to connect the SRAM generated by the memory compiler to the Ibex core and verify its functionality?

I am currently aiming to tape out a chip using SMIC's 180nm process. I am keeping the ibex core unchanged, but I need to embed SRAM on the chip. I use SMIC's memory compiler to generate the RAM's Verilog and liberty files, but I need to verify whether this SRAM can connect well with the ibex core and function properly. This is because the read/write timing of the SRAM generated by the memory compiler is different from that of prim_ram_2p. The prim_ram_2p can read out data in the current cycle, while the SRAM generated by the memory compiler requires a delay of one cycle to read out data. Therefore, I need to verify whether this SRAM works well; otherwise, I will need to design additional timing control logic.

I want to use the Ibex Simple System for verification. My steps are as follows:

1. Use the memory compiler to generate SRAM with width=32 and depth=1024*1024/4. By the way, are these parameter selections correct?
2. Replace prim_ram_2p with SRAM.v and connect the input and output port signals properly.
3. Compile the Ibex Simple System software to generate the vmem file.
4. Use ./build/lowrisc_ibex_ibex_simple_system_0/sim-vcs/lowrisc_ibex_ibex_simple_system_0 for simulation verification.

However, the simulation reports errors. It seems that the vmem is not read into the SRAM, and the instructions in the trace_core_00000000.log file are empty, showing INVALID. Is it possible that the SRAM cannot use the $readmemh command to load data? How should I proceed to verify it?

Start with the Ibex Simple System memory path, comparing prim_ram_2p with the mentioned SRAM.v ports and read timing. Run the listed simulation executable after generating the vmem file, then inspect the INVALID entries in trace_core_00000000.log. Done means the SRAM loads the program and the trace shows valid instruction execution.