Integration of 6T SRAM with the Ibex core

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We are trying to use our 6T SRAM design instead of the BRAM for simulation. I understand that we would still need the BRAM to copy the image(vmem or elf) into the memory. My idea is to copy the image into the BRAM and then write it into our SRAM design. I am considering instantiating our SRAM design instead of ram_1p/ram_2p in the RTL design. We are trying to use 1MB SRAM. I need some advice and help to understand the files I need to modify apart from the core files used by fusesoc, on how to load the image into the BRAM and then write it into our SRAM before the start of simulation. Please correct me if I am wrong here.

## My Environment

**EDA tool and version:**
I am using Verilator for simulation and Spike as ISS

**Operating system:**
The operating system is CentOS 7

**Version of the Ibex source code:**

Start by reviewing the ram_1p/ram_2p RTL references and the FuseSoC core files mentioned in the issue, then trace how Verilator and Spike are used with the vmem or ELF image. Determine the required path for loading the image into BRAM and transferring it to a 1MB 6T SRAM before simulation; the issue is done when that integration is specified and runs successfully.

Written by the indexing model from the issue text.