Illegal_reg_rv32e not updated on two consecutive multicycle invalid instructions
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Description
Observed Behavior
On sequence
jalr x2, 0(x16) Decode PC:32'h10080 Invalid correctly handled
jalr x2, 0(x16) Decode PC:32'h10000 Invalid not handled -> x2 wrongly updated
Expected Behavior
Steps to reproduce the issue
My Environment
EDA tool and version:
Operating system:
Version of the Ibex source code:
Configuration:
Two-stage pipeline without additional branch target ALU
RegFile : "ibex_pkg::RegFileFF"
BranchTargetALU : 0
WritebackStage : 0
https://github.com/lowRISC/ibex/commit/9e4a950aa6aa0e20eb638aeeb78743d4a9ddaaeb
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by reproducing the two consecutive jalr instructions with the stated two-stage configuration and compare register-file writes around Illegal_reg_rv32e. Inspect the Ibex RTL and verification tests for illegal multicycle instructions, using commit 9e4a950aa6aa0e20eb638aeeb78743d4a9ddaaeb as the reported source version. Done means the second invalid instruction no longer updates x2 and a regression test covers the sequence.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100