[rtl] Behaviour of debug single stepping with dummy instruction insertion may be surprising

I have observed a scenario where Ibex is single stepping whilst dummy instruction insertion is enabled. When a dummy instruction is inserted just as Ibex returns from debug mode to single step the next instruction, it single steps the dummy instruction instead. The depc is set correctly (i.e. it will rerun the instruction that should have been single stepped after a dret) but it could cause confusion for a debugger user and might break the debugger itself (that may reasonably assume a single step will always occur) but the instruction won't be incorrectly skipped.

This results in a mismatch with the cosim as it doesn't observe the dummy instruction on the RVFI interface so it sees the debug vector being re-entered without the single stepped instruction being executed.

To reproduce run:

make TEST=riscv_debug_single_step_test SEED=6250 ITERATIONS=1 WAVES=1 against commit 3384bf4c421781a2f5129307b912ac586c784977

There's three options I see here:

1. Declare this behaviour is reasonable
2. Force dummy instruction insertion to be disabled when running in single step
3. Alter the controller behaviour so we'll execute the dummy instruction and then single step

Option 3 is the most complex, option 2 should be pretty simple though does require an RTL change. Option 1 seems reasonable for OpenTitan (so no RTL fix needed for Earlgrey).

For any of these options we should look at DV in this area to ensure this scenario is properly covered.

Start by reproducing the scenario with make TEST=riscv_debug_single_step_test SEED=6250 ITERATIONS=1 WAVES=1 at commit 3384bf4c421781a2f5129307b912ac586c784977. Then inspect the debug single-step and dummy-instruction controller behavior and the related DV coverage. Done means the project has a decided policy for this case and the cosim/RVFI behavior and tests reflect it.