Store instructions do not always raise RV32E exceptions

Nobody has claimed this yet.

Store instructions will be decoded with `alu_op_b_mux_sel_o = OP_B_IMM`:
https://github.com/lowRISC/ibex/blob/1449ed5ea8f3d03127f7c3624e635e132830367d/rtl/ibex_decoder.sv#L778-L788

When `RV32E = 1` an illegal instruction exception should be raised if any of the registers used by a given instruction are outside of the `0-15` range. In the case of the store instruction this should apply to both the storage address and the stored value.

The existing logic in ibex will not enforce this since `alu_op_b_mux_sel_o = OP_B_IMM`:
https://github.com/lowRISC/ibex/blob/1449ed5ea8f3d03127f7c3624e635e132830367d/rtl/ibex_decoder.sv#L179-L183

Therefore in RV32E mode a store instruction may attempt to store a value from registers `16-31`, which is not well defined since the register file will not have those entries.

B-TYPE instructions, which have the same format, are likely unaffected since in their first cycle they do set `alu_op_{a,b}_mux_sel_o = OP_{A,B}_REG_{A,B}`.

Inspect rtl/ibex_decoder.sv at the cited store-decode and RV32E validation lines, then compare the handling with the B-TYPE instructions described in the issue. Confirm that RV32E store instructions reject out-of-range registers for both the storage address and stored value, while valid stores remain accepted.

Written by the indexing model from the issue text.