Spike not generating csrrw and compressed instructions
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- Dominant language
- SystemVerilog
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Description
Running RTL simulation at out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496/sim.log
Comparing traces for out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496
Collecting up results (report at out/seed-6496/regr.log)
0.00% PASS 0 PASSED, 1 FAILED
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Details of failing tests
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riscv_illegal_instr_test.6496
Test binary: out/seed-6496/instr_gen/asm_test/riscv_illegal_instr_test_0.o
UVM log: out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496/sim.log
RTL trace: out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496/trace_core_00000000.log
** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=43.
[FAILED]: sim error seen
0.00% PASS 0 PASSED, 1 FAILED
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start with the reported RTL simulation log at out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496/sim.log and compare it with the trace in the same directory. Inspect the generated binary at out/seed-6496/instr_gen/asm_test/riscv_illegal_instr_test_0.o; done means determining why csrrw and compressed instructions are not generated and making the illegal-instruction test pass.
Written by the indexing model from the issue text.
Assessment
- Domain
- testing
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100