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Hello, I'm trying to run synthesis with Vivado, and it shows some error messages like these:
```
[Synth 8-1766] cannot open include file prim_assert_dummy_macros.svh ["../ibex_rtl/prim_assert.sv":96]
[Synth 8-2841] use of undefined macro ASSERT ["../ibex_rtl/ibex_branch_predict.sv":91]
[Synth 8-2715] syntax error near ( ["../ibex_rtl/ibex_branch_predict.sv":91]

```

I also tried to set the file type, letting prim_assert_dummy_macros.svh become a "Global Include" file. After changing it, there are still some error messages:
```
[Synth 8-2379] near = `ASSERT_DEFAULT_RST : illegal macro parameter ["../ibex_rtl/prim_assert_dummy_macros.svh":12]
[Synth 8-2379] near = `ASSERT_DEFAULT_RST : illegal macro parameter ["../ibex_rtl/prim_assert_dummy_macros.svh":13]
[Synth 8-2379] near = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST : illegal macro parameter ["../ibex_rtl/prim_assert_dummy_macros.svh":14]
[Synth 8-2379] near = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST : illegal macro parameter ["../ibex_rtl/prim_assert_dummy_macros.svh":15]
[Synth 8-2379] near = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST : illegal macro parameter ["../ibex_rtl/prim_assert_dummy_macros.svh":16]
[Synth 8-2379] near = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST : illegal macro parameter ["../ibex_rtl/prim_assert_dummy_macros.svh":17]
[Synth 8-2379] near = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST : illegal macro parameter ["../ibex_rtl/prim_assert_dummy_macros.svh":18]
```

How can I make the synthesis work?

## My Environment

**EDA tool and version:**

Xilinx Vivado 2020.2

**Operating system:**

Ubuntu Linux 18.04

**Version of the Ibex source code:**

Reproduce the Vivado 2020.2 synthesis errors using the reported files: prim_assert.sv, prim_assert_dummy_macros.svh, and ibex_branch_predict.sv. Start by checking the Ibex synthesis flow and preprocessing settings; done means identifying a supported configuration or documenting the confirmed tool incompatibility.

Written by the indexing model from the issue text.