[dv] Improve instruction trace around faulting instructions
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- SystemVerilog
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Description
When an executed instruction generates a fault we suppress its destination register write. On the RVFI interface this mean setting the write register index to 0. On the instruction trace this results in seeing `x0` as the destination register, rather than the actual destination register. This can be confusing. We should improve our trace output to include the actual destination register in the printed instruction along with a note the write is suppressed due to a trap.
See https://github.com/lowRISC/opentitan/issues/13134 for an example of this issue.
Contributor guide
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the instruction-trace formatting and the faulting-instruction path described in the issue, using OpenTitan issue 13134 for example context. Done means a faulting instruction's trace shows its actual destination register and notes that the write was suppressed because of a trap.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot, observability
- Issue type
- Feature
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100